An SOI structure is composed of a thin semiconductor layer, which is located on a thin oxide layer. The oxide layer is typically formed as a buried oxide (BOX) and is, in turn, formed on a semiconductor layer, typically a silicon layer, that is, the silicon substrate, which usually has a thickness of 300 μm to 800 μm. The substrate only serves the purpose of handling the structure. The actual devices and device functions are realized in the semiconductor layer in the vicinity of the surface, similar to usual CMOS processes on homogenous silicon wafers.
A substantial difference in SOI technologies with respect to standard CMOS processes resides in the fact that devices are dielectrically isolated from each other by trenches which extend down to the insulation layer. Accordingly, a mutual electrical influence of the devices is significantly reduced. This dielectric isolation renders the SOI technology also suitable for high voltage applications.
It is advantageous when the devices are not coupled to each other via the substrate. Thus, certain non-desired substrate effects may be avoided, such as latch-up, significant reverse currents at elevated temperatures, increased parasitic capacitances at the source/bulk or drain/bulk-pn junctions.
U.S. Pat. No. 6,188,122 (Davari, IBM) discloses an SOI structure having a “capacitor” within the substrate and an FET (active device) in the upper silicon layer, column 4, line 40 onward. Conductive vias extend through the oxide layer (cf. 30), column 5, line 11 onward.